1. Field of the Invention
The present invention relates to a semiconductor device having a dual-gate thin film transistor and a method for manufacturing the semiconductor device. Specifically, the present invention relates to a semiconductor device in which a semiconductor film can be crystallized without being affected by a bottom gate electrode, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
FIG. 14 is a cross-sectional view illustrating a conventional dual-gate thin film transistor (TFT). This dual-gate TFT includes a substrate body 10A, a bottom gate electrode 33, a bottom gate insulating film 34, a semiconductor film 35, a top gate insulating film 36 that is formed of first and second insulating layers 36a and 36b, a top gate electrode 37, and an interlayer insulating film 38. The semiconductor film 35 includes a channel region 35a, a source region 35x that is formed of a low concentration source region 35b and a high concentration source region 35d, and a drain region 35y that is formed of a low concentration drain region 35c and a high concentration drain region 35e. Contact holes 13 and 14 are provided in the top gate insulating film 36 and the interlayer insulating film 38. A source line 6a and a data line 6b are electrically connected to the high concentration source region 35d and the high concentration drain region 35e of the semiconductor film 35 through the contact holes 13 and 14, respectively.
A method for forming the semiconductor film 35 included in the dual-gate TFT is described with reference to FIGS. 15A and 15B. FIGS. 15A and 15B are cross-sectional views illustrating a method for forming the semiconductor film of the dual-gate TFT shown in FIG. 14.
As shown in FIG. 15A, the light-transmitting substrate body 10A that is formed of a glass substrate or the like and has a surface cleaned by ultrasonic cleaning or the like is prepared. Over the entire surface of the substrate body 10A, a conductive film 72 having a light-shielding property is formed to a thickness of greater than or equal to 10 nm and less than or equal to 500 nm using a metal, such as aluminum, tantalum, molybdenum, titanium, or chromium, an alloy containing any of the above metals as its main component, or the like by a sputtering method or the like. Then, the conductive film 72 is patterned by a photolithography method, whereby a bottom gate electrode 33 having a light-shielding property is formed over the substrate body 10A.
Subsequently, over the substrate body 10A including the bottom gate electrode 33, a bottom gate insulating film 34 is formed to a thickness of greater than or equal to 10 nm and less than or equal to 50 nm using silicon oxide (SiO2), silicon nitride (Si3N4), or the like by a plasma CVD method or the like.
Subsequently, over the bottom gate insulating film 34, an amorphous semiconductor film 73 is formed to a thickness of greater than or equal to 10 nm and less than or equal to 100 nm using amorphous silicon (a-Si) by a plasma CVD method or the like, as shown in FIG. 15B. Subsequently, the amorphous semiconductor film 73 is heated by laser beam irradiation or the like to be polycrystallized, thereby forming a semiconductor film 24 formed of polycrystalline silicon. Subsequently, the polycrystalline semiconductor film 24 is patterned by a photolithography method, thereby forming the island-shaped semiconductor film 35 (e.g., see Patent Document 1 Japanese Published Patent Application No. 2005-79283, paragraphs 46 to 51, FIG. 5 and FIGS. 6A to 6E).